The present application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2002-181743 filed on Jun. 21, 2002, with the Japanese Patent Office, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention generally relates to clock signal generation apparatuses, and particularly relates to a clock signal generation apparatus which generates clock signals for the serial transfer of audio data.
2. Description of the Related Art
Methods for the serial transfer of audio data include a method that uses two types of clock signals, one being a bit clock signal for bit-by-bit transmission of data and the other being a word clock signal for switching over the left channel and the right channel of the audio data. In order to generate these audio clock signals, some methods employ a frequency divider and a counter circuit to generate each clock signal based on a master clock signal provided from an external source.
FIG. 1 is a circuit diagram showing an example of a construction of a related-art audio clock generation apparatus. In FIG. 1, a frequency divider is used to generate a bit clock signal, and a counter operates based on the generated bit clock signal to generate a word clock that is an upper bit of the count by the counter.
An audio clock generation circuit 10 of FIG. 1 includes a frequency divider 11, a counter 12, a D-flip-flop 13, a selector 14, a D-flop-flop 15, and an inverter 16. The frequency divider 11 divides the frequency of an audio master clock signal KFS that is provided from an external source, thereby generating a bit clock signal BCKO. The counter 12 receives the bit clock signal BCKO, and counts up in response to each positive transition of the bit clock signal BCKO. The selector 14 selects either the initial count or the current count by the counter 12 where the initial count is predetermined. The selected count is supplied to the counter 12. The counter 12 latches the count by a plurality of flip-flops as the count is supplied from the selector 14, and outputs the latched count after adding one thereto (i.e., +1). This output incremented by 1 is latched via the selector 14 at next timing, thereby achieving counting-up operations. The selector 14 selects the initial count of the counter in the initial state, and selects the count by the counter 12 after an input word clock signal LRCKI exhibits a positive transition. An upper bit of the count by the counter 12 is latched by the D-flop-flop 15 in synchronization with negative transition of the bit clock signal BCKO, followed by being output as the word clock signal LRCKO.
In this manner the bit clock signal BCKO and the word clock signal LRCKO are generated as shown in FIG. 2. The initial value of the counter is set such that the upper bit of the count latched by the D-flop-flop 15 becomes 1 when the count is incremented by 1 after a positive transition of the input word clock signal LRCKI. Accordingly, the word clock signal LRCKO rises immediately after the input word clock signal LRCKI has a positive transmission.
The counter 12 keeps counting by recursively returning to zero, so that the HIGH period and the LOW period of the word clock signal LRCKO each being a predetermined duration are alternated. In the related-art configuration shown in FIG. 1, the word clock signal LRCKO is synchronized at the time the input word clock signal LRCKI first rises to HIGH. Thereafter, alternation of the HIGH period and the LOW period of the word clock signal LRCKO is controlled by the timing of the bit clock signal generated by the frequency divider 11. In this manner, the timing of the word clock signal LRCKO is independent of the changes of the input word clock signal LRCKI, except for its initial setting.
In the related-art construction as described above, a displacement in the positive transition of the input word clock signal LRCKI will result in the input word clock signal LRCKI and the word clock signal LRCKO being displaced relative to each other in terms of their phases. In order to obviate this, the counter may be reset by hardware resetting or software resetting triggered from the exterior, thereby reestablishing the synchronization of the clock generation so as to correct the phase displacement. In this case, however, there is a need to trigger hardware resetting or software resetting from the exterior of the device by detecting the timing displacement of the input word clock signal LRCKI. This requires complex control and large circuit size.
Accordingly, there is a need for a clock signal generation apparatus which can generate a word clock signal that follows timing changes, without requiring externally triggered hardware resetting or software resetting.
It is a general object of the present invention to provide a clock signal generation apparatus that substantially obviates one or more problems caused by the limitations and disadvantages of the related art.
Features and advantages of the present invention will be presented in the description which follows, and in part will become apparent from the description and the accompanying drawings, or may be learned by practice of the invention according to the teachings provided in the description. Objects as well as other features and advantages of the present invention will be realized and attained by a clock signal generation apparatus particularly pointed out in the specification in such full, clear, concise, and exact terms as to enable a person having ordinary skill in the art to practice the invention.
To achieve these and other advantages in accordance with the purpose of the invention, the invention provides a clock generation apparatus, including a first clock generation circuit which generates a clock signal by making state transition in synchronization with a master clock signal after exiting from a predetermined state in response to a timing signal supplied from an exterior of the apparatus, a counter which counts clock pulses of the master clock signal after exiting from a reset state in response to the timing signal, and a reset circuit which resets the counter and sets the first clock generation circuit in the predetermined state in response to the count of the counter reaching a first predetermined value.
In the clock generation apparatus as described above, the first clock generation circuit and the counter are set and reset, respectively, in response to the count reaching the predetermined value, and, then, start operating by exiting from the set state and the reset state, respectively, in response to the timing signal supplied from the exterior. Accordingly, the first clock generation circuit and the counter are set and reset, respectively, upon the completion of counting the clock pulses of the master clock signal as many as the count corresponds to the duration of the L channel and R channel, and an operation that generates the clock signal can be started by exiting from the set state and the reset state in response to the input word clock signal LRCKI. This makes it possible to generate an output clock signal that follows timing changes of the input word clock signal LRCKI.
According to another aspect of the invention, the clock generation circuit as described above further includes a second clock generation circuit which generates another clock signal by making state transition in synchronization with the master clock signal after exiting from a reset state in response to the timing signal.
In the clock generation circuit as described above, the first and second clock generation circuits are sued to generate a word clock signal and a bit clock signal that follow timing changes of the input word clock signal LRCKI.
Other objects and further features of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings.